Embedded systems design in the new millennium (panel session).A. Richard Newton, Walden C. Rhines, Sünke Mehrgardt, Henry Samueli, Tudor BrownDAC2000•Cited by 0Gemini InsightCite
Automatic Building of Graphs for Rectangular Dualisation.Marwan A. JabriDAC1988•Cited by 0Gemini InsightCite
An intelligent module generator environment.Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De ManDAC1986•Cited by 6Gemini InsightCite
Functional Timing Analysis for IP Characterization.Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. SakallahDAC1999•Cited by 14Gemini InsightCite
ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models.Ying Liu, Lawrence T. Pileggi, Andrzej J. StrojwasDAC1998•Cited by 8Gemini InsightCite
Resistance Extraction and Resistance Calculation in GOALIE?Kuang-Wei ChiangDAC1989•Cited by 12Gemini InsightCite
A new approach to latency insensitive design.Mario R. Casu, Luca MacchiaruloDAC2004•Cited by 83Gemini InsightCite
Device/circuit interactions at 22nm technology node.Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar GuptaDAC2009•Cited by 9Gemini InsightCite
Robust gate sizing by geometric programming.Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. SapatnekarDAC2005•Cited by 127Gemini InsightCite
Can pin access limit the footprint scaling?Xiang Qiu, Malgorzata Marek-SadowskaDAC2012•Cited by 15Gemini InsightCite
Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models.Lucas Roquet, Fernando Fernandes dos Santos, Paolo Rech, Marcello Traiola, Olivier Sentieys, Angeliki KritikakouDAC2024•Cited by 8Gemini InsightCite
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SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture.Fangxin Liu, Wenbo Zhao 0005, Zongwu Wang, Yongbiao Chen, Tao Yang 0031, Zhezhi He, Xiaokang Yang 0001, Li Jiang 0002DAC2022•Cited by 17Gemini InsightCite
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Hawkware: Network Intrusion Detection based on Behavior Analysis with ANNs on an IoT Device.Sunwoo Ahn, Hayoon Yi, Younghan Lee, Whoi Ree Ha, Giyeol Kim, Yunheung PaekDAC2020•Cited by 10Gemini InsightCite
Hybrid hierarchical timing closure methodology for a high performance and low power DSP.Kaijian Shi, Graig GodwinDAC2003•Cited by 1Gemini InsightCite
Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device Modeling.Chanwoo Park, Junghwan Park, Premkumar Vincent, Hyunbo ChoDAC2024•Cited by 3Gemini InsightCite
Placement of variable size circuits on LSI masterslices.K. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. HattonDAC1981•Cited by 0Gemini InsightCite
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.Yuan Pu 0001, Fangzhou Liu, Yu Zhang 0189, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu 0001DAC2024•Cited by 2Gemini InsightCite